The present invention relates to a DRAM cell arrangement, that is to say a memory cell arrangement with dynamic random access, in which a memory cell has three transistors.
In DRAM cell arrangements, at the present time use is made almost exclusively of so-called single-transistor memory cells. A single-transistor memory cell has a read-out transistor and a storage capacitor. The information is stored in the storage capacitor in the form of an electric charge, which represents a logic value, 0 or 1. By driving the read-out transistor via a word line, this information can be read out via a bit line. The electric charge stored in the storage capacitor drives the bit line in this case.
Since the storage density increases from memory generation to memory generation, the required area of the single-transistor memory cell must be reduced from generation to generation. This leads to fundamental technological and physical problems. For example, despite a smaller area of the single-transistor memory cell, the storage capacitor must be able to store a minimum amount of electric charge in order to be able to drive the bit line.
This problem is circumvented in an alternative DRAM cell arrangement in which so-called gain cells are used as memory cells. Here, too, the information is stored in the form of an electric charge. However, the electric charge does not have to drive a bit line directly, but rather is stored in a gate electrode of a transistor and serves only to control the latter, for which purpose a very small amount of electric charge is actually sufficient.
A gain cell having three components, namely a first transistor, a second transistor and a diode, is described in Microelectronic Engineering 15 (1991) pages 367-370. The electric charge is stored in a second gate electrode of the second transistor. The electric charge is stored using the first transistor and the diode. For this purpose, the second gate electrode is connected to the diode, the diode is connected to a second source/drain region of the second transistor and to a first source/drain of the first transistor, a first source/drain region of the second transistor is connected to a voltage source and a second source/drain region of the first transistor is connected to a bit line. For the purpose of storage, a first gate electrode of the first transistor is driven via a word line. The amount of electric charge and thus the information stored in the second gate electrode is determined by a voltage on the bit line. The diode is forward-biased in this case. The information is read out by driving the first gate electrode of the first transistor via the word line. The amount of electric charge and thus the information stored in the second gate electrode determines whether or not current flows in the bit line. The diode is reverse-biased in this case.